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Avoid Design Problems Using Worst Case Analysis Calculations

November 3, 2022 @ 12:00 pm - 1:00 pm

As a design engineer how do we avoid getting a call on a Friday afternoon, telling us that the circuit we
designed is failing in production test, and the line is shut down? This happens in manufacturing all too
often, because of part tolerances, and poor design fundamentals. To most of us this is a nightmare
scenario, but it doesn’t have to be. You can avoid this scenario by understanding the key
parameters/tolerances of the components being used in the circuitry you are designing, and how to
perform worst case analysis on that circuitry. Using design examples we will go through in detail what to
analyze, and how to perform the calculations. The discussion will include detail on op-amps, voltage
regulators, resistors, capacitors, MOSFET’s, diodes, and generalized IC’s.

Speaker(s): Louis Diana,

Bldg: Hauppauge Radisson, 110 Motor Parkway, Hauppauge, New York, United States

Details

Date:
November 3, 2022
Time:
12:00 pm - 1:00 pm
Event Category:
Website:
https://events.vtools.ieee.org/m/333416

Organizer

[email protected]_edu
Email:
fang_luo@stonybrook_edu

Venue

Bldg: Hauppauge Radisson, 110 Motor Parkway, Hauppauge, New York, United States
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