Electrostatic Discharge (ESD) Protection in 28-nm CMOS Technology Node and Beyond:

Electrostatic discharge (ESD) is one of the most prevalent threats to the reliability of electronic components. It is an event in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and hence more than 35% of chip damages can be attributed to the ESD event.  As such, designing on-chip ESD structures to protect integrated circuits against the ESD stress is a high priority in the semiconductor industry. The continuing advancement in semiconductor technology makes the ESD-induced failures even more prominent. In fact, many semiconductor companies worldwide are having difficulties in meeting the increasingly stringent ESD protection requirements for various tech applications, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical and essential factor to the well-being and commercialization of next-generation electronics.

An overview on the ESD sources, models, protection schemes, and testing will first be given in this talk. This is followed by the introduction of ESD protection designs in the 28-nm CMOS process, and then the exploration and evaluation of ESD protection solutions in the sub 20-nm emerging Si FinFET and nanowire technologies. Status, challenges and difficulties associated with the ESD design and optimization for these technologies will be addressed. 

Speaker(s): Prof. Juin Liou,

Location:
Room: 414
Bldg: Schapiro-CEPSR
530 W120th Street
Columbia University
New York, New York
10027