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From Top-Level Design Specification to Detail Design

May 4 @ 12:45 pm - 1:45 pm

This discussion will focus on the process of breaking down top-level system specifications into detailed design requirements that an individual designer can address. It will talk about the systematic decomposition and allocation processes, from top-level requirements decomposition to functional identification and allocation, to functional decomposition, and finally to the physical allocation to a design entity… be it for microwave, analog, digital, or signal processing hardware, or FPGA or embedded processor code. It will use the introduction of Direct Digital Synthesizers into historically analog equipment as an example of the process. This discussion is appropriate for both practitioners as well as undergraduate engineering students.

Co-sponsored by: NYIT College of Engineering and Computer Science

Speaker(s): Ed Palacio,

New York, New York, United States, Virtual: https://events.vtools.ieee.org/m/263299

Details

Date:
May 4
Time:
12:45 pm - 1:45 pm
Event Category:
Website:
https://events.vtools.ieee.org/m/263299

Organizer

robdif@ieee_org
Email:
robdif@ieee_org

Venue

New York, New York, United States, Virtual: https://events.vtools.ieee.org/m/263299
New York, New York, United States, Virtual: https://events.vtools.ieee.org/m/263299 + Google Map

IEEE Region 1 Website