Open Source Chip Design

Lowering the barriers to chip design using OpenFASOC: Fully Autonomous System-on-Chip (FASoC) tool is a DARPA-funded project within the IDEA program. Its main objective is to address the need for analog compilers. The framework relies on the place and route digital flow which has long been extensively automated while most analog flows are still extremely reliant on manual design. This lack of analog automation tools leads to long design cycles and costs. FASoC addresses this need and uses a cell-based analog design generation methodology to generate different analog and mixed-signal (AMS) blocks (i.e., PLL, LDO, DC-DC converters, Temperature Sensors, etc.).

A few SoCs have been taped out in the SkyWater 130 nm, BI-CMOS 130 nm, TSMC 65 nm and Globalfoundries 12 nm foundry process nodes. OpenFASOC has been built on top of OpenROAD for push-button layout generation as part of the current open source effort. This talk will go through a few of our open-source analog generators (Temperature Sensor, Switched-Cap DC-DC Converter, etc.), our implemented designs in Google’s free shuttles MPW-I / II and our GF12LP tapeout of the OpenTitan SoC which heavily used open source tooling.

Co-sponsored by: IEEE Consultants’ Network of Northern New Jersey

Speaker(s): Dr. Saligane,

Agenda:
6:30 PM to 8:30 PM – Presentation

8:30+ networking session on Zoom

Virtual: https://events.vtools.ieee.org/m/328368