RowHammer, RowPress and Beyond: Can We Be Free of Bitflips (Soon)?

We will examine the RowHammer problem in Dynamic Random Access Memory (DRAM), the first example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. RowHammer is the phenomenon that repeatedly accessing a row in a modern DRAM chip predictably causes bitflips in physically-adjacent rows. Building on our initial fundamental work that appeared at ISCA 2014, Google Project Zero demonstrated that this hardware phenomenon can be exploited by user-level programs to gain kernel privileges. Many other works demonstrated other attacks exploiting RowHammer, including remote takeover of a server vulnerable to RowHammer, takeover of a mobile device by a malicious user-level application, and destruction of predictive capabilities of commonly-used deep neural networks.

Unfortunately, the RowHammer problem still plagues cutting-edge DRAM chips, DDR4 and beyond. Based on our recent characterization studies of more than 1500 DRAM chips from six technology generations that appeared at ISCA 2020 and MICRO 2021, we show that RowHammer at the circuit level is getting much worse, newer DRAM chips are much more vulnerable to RowHammer than older ones, and existing mitigation techniques do not work well. We also show that existing proprietary mitigation techniques employed in DDR4 DRAM chips, which are advertised to be Rowhammer-free, can be bypassed via many-sided hammering (also known as TRRespass & Uncovering TRR).

In this talk, we will provide an overview of RowHammer research in academia and industry, with a special focus on recent works that rigorously analyze real chip characteristics and introduce promising solution ideas. We will discuss the effect of RowHammer on High-Bandwidth Memory (HBM) chips and introduce and analyze RowPress, which is a fundamentally different read disturbance phenomenon that also affects all DRAM chips. RowPress greatly (e.g., by 100X) reduces the activation count required to induce bitflips, by keeping an activated row open for a long time. We will also discuss what other problems may be lurking in DRAM and other types of memory, which can potentially threaten the foundations of reliable and secure systems, as memory technologies scale to higher densities. We will conclude by describing and advocating a principled approach to memory robustness (including reliability, security, safety) research that can enable us to better anticipate and prevent such vulnerabilities.

A short accompanying paper, which appeared at ASP-DAC 2023, can be found here and serves as recommended reading:
“Fundamentally Understanding and Solving RowHammer”
https://arxiv.org/abs/2211.07613

Co-sponsored by: IEEE North Jersey Section

Speaker(s): Onur Mutlu

Agenda:
Event Time: 2:45 PM to 4:30 PM

ECE 202, NJIT, Newark

3:45 PM to 3:00 PM Refreshments and Networking

3:00 PM to 4:30 PM Talk by Professor Onur Mutlu of ETH/Carnegie Mellon/Stanford

Seminar is in ECEC 202. All Welcome: There is no fee/charge for attending IEEE technical seminar. You don’t have to be an IEEE Member to attend. Refreshments are free for all attendees. Please invite your friends and colleagues to take advantage of this talk.

Room: 202, Bldg: Electrical and Computer Engineering, 154 Summit Street, Newark, NJ 07102, NJIT, Newark, New Jersey, United States, 07102