Scalable Deep Neural Network Hardware with Multi-Chip Modules

Deep Neural Network (DNN) use cases range have diverse performance and power targets. These are highly compute-intensive and have growing demands as DNN models get larger and more complex. Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. While accelerators fabricated on a single monolithic chip are optimal for specific network sizes, MCM-based architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. This talk explores the benefits of using MCMs with fine-grained chiplets for scaling DNN inference. It presents a 36-chiplet prototype MCM system for deep-learning. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. Communication energy is minimized with large on-chip distributed weight storage and a hierarchical network-on-chip and network-on-package, and inference energy is minimized through extensive data reuse.

Speaker(s): Dr Rangharajan Venkatesan,

Room: B205, Bldg: Department of Electrical & Computer Engineering, Engineering Quadrangle, Olden Street, Princeton, New Jersey, United States, 08544