Techniques for High-Performance Successive-Approximation-Register ADCs

The demand for high-speed, low-power analog-to-digital converters (ADCs) for high-speed wireline transceivers and mmWave radios continues to grow unabated, driven in part by advances in DSP-based architectures and technology-scaling benefits in digital circuits. Recent works on high-speed ADCs operating at > 10 GHz with 6 to 8 bits of resolution have made tremendous progress, but significant challenges remain. This talk discusses techniques to achieve simultaneous high speed and high power efficiency by using the time-interleaved successive-approximation-register (SAR) architecture. We present “constant-matching scaling” and “grouped capacitors” for the digital-to-analog-converter (DAC) to aggressively reduce the capacitance and increase the speed. The ADC also demonstrates a “dual-path” bootstrapped switch to increase the sampling spurious-free dynamic range (SFDR). Employing the above and other low-power, high-speed techniques, the proposed SAR ADC obtains a single-channel speed of 1.25-GHz without the need for pipelining. The ADC uses only 8X time-interleaving to achieve an overall sampling rate of 10 GHz and a signal-to-noise-and-distortion ratio (SNDR) of 36.9 dB at Nyquist while consuming 21 mW.

Speaker(s): Shiuh-hua Wood Chiang,

Room: 240, Bldg: Electrical Engineering, 94 Brett Road, Piscataway, New Jersey, United States, 08854