Abstract: While silicon scaling has reached astonishing levels over the last half century, there has not been a corresponding level of scaling in electronic packaging technology. However, Artificial Intelligence (AI) architectures are now changing the landscape, increasingly moving us towards advanced packaging technology, especially Heterogeneous Integration (HI). What are these unique requirements of AI which are driving the need for HI? What are some of the unique challenges in semiconductor and packaging technologies that must be overcome to make this successful? This seminar will discuss key HI methods including interposers, fan out wafer level processing, silicon bridges, and 3D integration. We will look at their attributes as well as their challenges, to determine how they can be leveraged to achieve AI architectures. Speaker(s): Mukta Farooq, Agenda: 12:00 noon: pizza is served 12:15PM: talk begins 1PM: Q&A, discussion, refreshments Room: GOL-2400, Bldg: Golisano Hall (Computing), Rochester Institute of Technology, Rochester, New York, United States, 14623