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Chiplet Design and Heterogeneous Integration Packaging

March 26 @ 14:30 - 15:45

Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have generated lots of traction lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. Speaker(s): John H Lau, Agenda: 6:10 PM: Networking and Refreshments 6:30 PM: Announcements and Speaker Introduction 6:35 PM: DL 7:30 PM: Questions and Answers 7:45 PM: Adjourn ============ In this lecture, the following topics will be covered. System-on-Chip (SoC) Why Chiplet Design? Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split Chip partition and Heterogeneous Integration Chip split and Heterogeneous Integration Advantages and Disadvantages Lateral Communication between Chiplets (e.g., Bridges) Bridge Embedded in Build-up Package Substrate Bridge Embedded in Fan-Out EMC with RDLs UCIe Hybrid Bonding Bridge Chiplet Design and Heterogeneous Integration Packaging – Multiple System and Heterogeneous Integration Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration) Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration) Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration) Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration) Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration) Summary Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging Trends in Chiplet Design and Heterogeneous Integration Packaging Who Should Attend? If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and the books by the lecturer. Room: 201 Bluemont Room, Bldg: Arlington Central Library, 1015 North Quincy Street, Arlington, Virginia, United States, 22201, Virtual: https://events.vtools.ieee.org/m/408058