IEEE North Jersey Section

Planned by the Region 1 and Region 2 Computer Chapters and the local NJ Coast Instrumentation & Measurements / Computer Joint Chapter, and Region 1 & 2 Professional Activities Events, and associates: Join in for a Presentation by Dr Giovanni Vannucci: Total Eclipse of the Sun: A Day at the Museum at the AT&T Labs Science & Technology Center & Museum in Middletown New Jersey. Prepare for the rare event: the 8 April Total Eclipse of the Sun that will pass through our Regions. The 26 March Event will begin at 12 Noon with a Meet and Greet Dr Giovanni Vannucci, Lunch with Leaders & Luminaries, Networking, Watch Party, STEM students, Museum Tours, and social networking. The Live Event will wind down with Cupcakes and Cookies at 3pm. Information from NASA: The Monday, April 8, 2024, total solar eclipse will cross North America, passing over Mexico, the United States, and Canada. The total solar eclipse will begin over the South Pacific Ocean. Weather permitting, the first location in continental North America that will experience totality is Mexico’s Pacific coast at around 11:07 a.m. PDT. https://science.nasa.gov/eclipses/future-eclipses/eclipse-2024/where-when/ Speaker(s): Dr Giovanni Vannucci, Agenda: 26 March 2024 12 Noon Welcome to the AT&T Labs Science and Technology Innovation Center and Museum Meet & Greet the Speaker, Dr Giovanni Vannucci, Social Experience Lunch with Leaders and Luminaries, STEM Guests Presentation by Dr Giovanni Vannucci Discussions with Colleagues and Watch Party Tour of the Museum with Expert Docents 3.00 PM Formal Program winds down with cupcakes Bldg: A, AT&T Science and Technology Innovation Center and Museum, 200 S Laurel Ave., Middletown Township, New Jersey, United States

Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have generated lots of traction lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. Speaker(s): John H Lau, Agenda: 6:10 PM: Networking and Refreshments 6:30 PM: Announcements and Speaker Introduction 6:35 PM: DL 7:30 PM: Questions and Answers 7:45 PM: Adjourn ============ In this lecture, the following topics will be covered. System-on-Chip (SoC) Why Chiplet Design? Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split Chip partition and Heterogeneous Integration Chip split and Heterogeneous Integration Advantages and Disadvantages Lateral Communication between Chiplets (e.g., Bridges) Bridge Embedded in Build-up Package Substrate Bridge Embedded in Fan-Out EMC with RDLs UCIe Hybrid Bonding Bridge Chiplet Design and Heterogeneous Integration Packaging - Multiple System and Heterogeneous Integration Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration) Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration) Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration) Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration) Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration) Summary Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging Trends in Chiplet Design and Heterogeneous Integration Packaging Who Should Attend? If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and the books by the lecturer. Room: 201 Bluemont Room, Bldg: Arlington Central Library, 1015 North Quincy Street, Arlington, Virginia, United States, 22201, Virtual: https://events.vtools.ieee.org/m/408058